Tuesday, July 6, 2021

PCB DESIGN USING KI-CAD PART1 (BEGINNERS)

KI-CAD FOR BEGINNERS PART 1

Posted By : Jaydeep Shah (Download pdf)

 

KiCad is a free software suite for electronic design automation. It facilitates the design of schematics for electronic circuits and their conversion to PCB designs. KiCad was originally developed by Jean-Pierre Charras. It features an integrated environment for schematic capture and PCB layout design.

KiCad does not present any board-size limitation and it can easily handle up to 32 copper layers, up to 14 technical layers and up to 4 auxiliary layers. KiCad can create all the files necessary for building printed boards, Gerber files for photo-plotters, drilling files, component location files and a lot more.

Being open source (GPL licensed), KiCad represents the ideal tool for projects oriented towards the creation of electronic hardware with an open-source flavour.

 

 It is possible to make single/multiple layers of PCB design using ki-cad and its easy because of open source community support with lots of inbuilt library and footprints. 


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Thursday, January 30, 2020

PFM - PULSE FREQUENCY MODULATION Techniques in SMPS IC

PULSE FREQUENCY MODULATION (PFM) In DC-DC Switching Regulator.


Subject : SMPS Designing / Power Electronics / DC-DC switching Regulator
Jaydeep Shah (EC Engineer)


PDF DOWNLOAD LINK : CLICK HERE --> PDF FILE 

CHAPTER – BASIC TERMINOLOGY OF PFM SMPS IC


Why this consept important??  à Now a days designers focus on the design of the DC-DC converter to ensure that it consumes as little current as possible during no-load conditions. All DC-DC converters, even during standby,can consume significant quiescent current (Quiescent Current can be defined as the amount of current used by an IC when in a Quiescent state. The Quiescent state being any period of time when the IC is in either a no load or non-switching condition).



One commercial power-supply module (EX: the RECOM® R-78A3.3-1OR), for example, draws about 7mA under no-load conditions. However, with some attention to topology and careful design, an isolated DC-DC converter module with a no-load current drain of less than 1mA can be implemented.
 

These converters (Available in market) traditionally employ pulse-width-modulation controllers. However, PWM controllers always have an active oscillator (RC), even when there is no load, and that oscillator continually draws current from the battery , This is one of the disadvantage of PWM Controller.

Before starting PFM, Need to understand what is PFM ?….
PWM Control :

The oscillator frequency is constant and the pulse width (ON time) changes according to the amount of output load.



VFM Control

The pulse width (ON time) is constant and the oscillator frequency changes according to the amount of output load.




Oscillator Frequency
Pulse Width
(Duty)
Light Load Condition
Noise
Suppression*1
Efficiency
Ripple Voltage
VFM Control
Change
Constant
Good
High
Difficult
PWM Control
Constant
Change
Not Good
Low
Easy



n  Noise suppression of VFM control can be difficult because oscillator frequency is inconsistent and it affects noise level.
n  Noise suppression of PWM control is relatively easier because oscillator frequency is constant and it does not affect noise level.
Now a days –> DC-DC converters include the products that are only operated by PWM control and the products that can be automatically switched between PWM mode and VFM mode according to the load condition.
Two Methods for Feed backing the Output :
A transformer provides the isolation, but the challenge is to feed back the voltage reference from the secondary side to the primary side without breaking the isolation. The most common approach solves the problem by using either an auxiliary winding or an optocoupler.

Function of Leading Edge blanking (LEB)  :
Leading edge blanking circuit on current sense input could remove the signal glitch due to snubber circuit diode reverse recovery and thus greatly reduces the external component count and system cost in the design.
n  Each time the power MOSFET is switched on, a turn-on spike will inevitably occur at the Sense pin, which would disturb the internal signal from the sampling of the RSENSE. There is a 300ns ( This time period depends on manufacturer and internal structure – near 30 ms in SMPS IC) leading edge blanking time built in to avoid the effect of the turn-on spike, and the power MOSFET cannot be switched off during the moment. So that the conventional external RC filtering on sense input is no longer required.

n  In short during this time period power supply does not take any signal for comparison purpose.
 




 Sometimes, the RC delay circuit (Low pass Filter) is insufficient for removing the false noise signals at the input of the PWM comparator. when the gate drive switches from low to high and the parasitic capacitance from the gate to the source of Q1 is charging. Depending on the values of Gate Resistor and Current sense resistor , a large-enough leading-edge voltage spike could falsely trigger the PWM comparator at the ISENSE pin. This problem is common in isolated dc/dc power converters. 



To remove false triggering from the PWM comparator, it is desirable to blank out the leading-edge spikes that appear on the current-sense signal.Using three to five more components (like BJT and RC network) with RC low pass filter we can implemented this circuit, and now this is internal features of many IC.

·         Quasi Resonant :
Quasi-resonant switching, compared to the traditional continuous and discontinuous modes of operation in a flyback converter, cuts turn-on losses at the power switch, thus increasing efficiency and lowering device temperatures. Its disadvantage, that of higher losses at light loads, is eliminated by the frequency-clamp circuit used in today's controllers and integrated power switches.


Quasi-resonant conversion works in quite a different way than the well-known resonant converter to cut losses. Now consider Figure 1, which shows the waveforms at the drain in a current-mode flyback converter operating in the discontinuous conduction mode. Only one gate pulse has been applied. During the first time interval, the drain current ramps up until the desired current level is reached. The power switch then turns off. The leakage inductance in the flyback transformer rings with the node capacitance. This causes a leakage inductance spike, which is limited by a clamp circuit. After the inductive spike has diminished, the drain voltage returns to the input voltage plus the reflected output voltage. The drain voltage would immediately drop to the bus voltage when the current in the output diode drops to zero if the effect of the primary inductance and the node capacitance were ignored.
In quasi-resonant switching, the device does not have a fixed switching frequency. Instead, the controller waits for one of the troughs in the drain voltage and then switches on.


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Thanks :
Jaydeep Shah 
Electronics & Communication Engineer
Ahmedabad -  India
Email :  radhey04ec@gmail.com

Friday, September 6, 2019

MOSFET in Power supply Application



MOSFET & It's Application in SMPS : 

Jaydeep Shah (06- sep 2019 )



MOSFETs are available in two basic forms:
  • Depletion Type: The transistor requires the Gate-Source voltage (VGS) to switch the device “OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed” switch.
  • Enhancement Type: The transistor requires a Gate-Source voltage(VGS) to switch the device “ON”. The enhancement mode MOSFET is equivalent to a “Normally Open” switch.
Depending upon the type of materials used in the construction, and the type of operation, the MOSFETs are classified as in the following figure.

The N-channel MOSFETs are simply called as NMOS. The symbols for N-channel MOSFET are as given below.
The P-channel MOSFETs are simply called as PMOS. The symbols for P-channel MOSFET are as given below
 A lightly doped P-type substrate is taken into which two heavily doped N-type regions are diffused, which act as source and drain. Between these two N+ regions, there occurs diffusion to form an Nchannel, connecting drain and source. (Diffusion is net movement of anything from a region of higher concentration to a region of lower concentration.)


A thin layer of Silicon dioxide (SiO2) is grown over the entire surface and holes are made to draw ohmic contacts for drain and source terminals.

It is a four-terminal device with source(S), gate (G), drain (D) and body (B) terminals. The body is frequently connected to the source terminal, reducing the terminals to three. It works by varying the width of a channel along which charge carriers flow (electrons or holes).
The charge carriers enter the channel at source and exit via the drain. The width of the channel is controlled by the voltage on an electrode is called gate which is located between source and drain.

In general, any MOSFET is seen to exhibit three operating regions

  1. Cut-Off Region
    Cut-off region is a region in which the MOSFET will be OFF as there will be no current flow through it. In this region, MOSFET behaves like an open switch and is thus used when they are required to function as electronic switches.
  2. Ohmic or Linear Region
    Ohmic or linear region is a region where in the current IDS increases with an increase in the value of VDS. When MOSFETs are made to operate in this region, they can be used as amplifiers.
  3. Saturation Region
    In saturation region, the MOSFETs have their IDS constant in spite of an increase in VDS and occurs once VDS exceeds the value of pinch-off voltage VP. Under this condition, the device will act like a closed switch through which a saturated value of IDS flows. As a result, this operating region is chosen whenever MOSFETs are required to perform switching operations.
Figure 1a shows the transfer characteristics (drain-to-source current IDS versus gate-to-source voltage VGS) of n-channel Enhancement-type MOSFETs. From this, it is evident that the current through the device will be zero until the VGS exceeds the value of threshold voltage VT. This is because under this state, the device will be void of channel which will be connecting the drain and the source terminals. Under this condition, even an increase in VDS will result in no current flow as indicated by the corresponding output characteristics (IDS versus VDS) shown by Figure 1b. As a result this state represents nothing but the cut-off region of MOSFET’s operation.

Next, once VGS crosses VT, the current through the device increases with an increase in IDS initially (Ohmic region) and then saturates to a value as determined by the VGS (saturation region of operation) i.e. as VGS increases, even the saturation current flowing through the device also increases. This is evident by Figure 1b where IDSS2 is greater than IDSS1 as VGS2 > VGS1, IDSS3 is greater than IDSS2 as VGS3 > VGS2, so on and so forth. Further, Figure 1b also shows the locus of pinch-off voltage (black discontinuous curve), from which VP is seen to increase with an increase in VGS.



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·         SELECTION OF THE MOSFET :  



Voltage and Current Ratings

The drain-source voltage VDSS rating is important in selecting MOSFETs. Application of a voltage exceeding VDSS might result in the destruction of a MOSFET. It is necessary to choose MOSFETs with a VDSS sufficiently higher than the voltage at which they will actually be used. However, MOSFETs with high VDSS ratings tend to have large on-state resistance, RDS(ON). A downside of using such MOSFETs is increased conduction loss. If you select MOSFETs according to possible peak surge voltage, you could end up opting for devices with large on-state resistance. To address this situation. Generally, on-state resistance determines the upper limit of the drain current ID. Ensure that not only the loss calculated as ID2×RDS(ON), the permissible power dissipation but also a temperature rise due to heating does not cause the device to exceed its operating temperature range.

Switching Speed

When a power MOSFET switches at a high frequency, its switching loss accounts for a significant portion of total loss. To reduce total loss for high frequency switching applications, high speed power MOSFETs should be used.

What is MOSFET Switching Time?

The MOSFET will turn ON or OFF after the Gate voltage turns ON/OFF. The time in between turning ON or OFF is called the switching time.

 EX:

VGS threshold: VGS(th) :

VGS(th) is the voltage required between the Gate and Source to turn ON the MOSFET.In other words, supplying a voltage greater than VGS(th) will turn ON the MOSFET.
To determine the amount of current that flows through the MOSFET when ON it is necessary to refer to the specifications and electrical characteristics for each element.
Table 1 lists the relevant electrical characteristics. In the case of VDS=10V a threshold voltage of between 1.0V and 2.5V is required for an ID of 1mA.


Parasitic Capacitance


Parasitic capacitance exists in power MOSFETs as shown in Figure 1.
Sometimes known as stray capacitance, parasitic capacitance is unavoidable and typically unwanted that exists between the parts of an electronic component or circuit simply because of how close they are to one another. Capacitance is the ability of a system to store an electric charge.

The Gate terminal in a MOSFET is isolated from the other terminals by an oxide film. The silicon under the gate has the opposite polarity to the drain and source which results in the formation of PN junctions (diode) between the Gate, Drain and Source regions. Cgs and Cgd are the capacitance of the oxide layers, while Cds is determined by the junction capacitance of the internal diode.




Switching Time and Drive Conditions :

Bipolar transistors need a large base current to maintain low on-state voltage. In contrast, since power MOSFETs are voltage-controlled devices, they can be driven just by charging gate capacity, and are therefore a low in power consumption.

Note, however, that power MOSFETs have a slightly large input capacitance Ciss. Thus, for high speed switching applications, it is necessary to quickly charge the input capacitance from a low-impedance signal source.

Low-impedance drive is required to reduce turn-on time. However, the use of a high gate voltage results in the much charging of gate-source capacitance, resulting in an increase in td (off).
Switching time can be controlled via gate resistance. If you want to change the turn-on and turn-off switching speeds separately, you can use diodes to change the gate resistance values for turn-on and turn-off. Figure 2.3 shows some examples.


Gate Drive Resistor

RG is the gate driver resistor for the power switch, MOSFET. The selection of this resistor value must be done in conjunction with EMI compliance testing and efficiency testing. Using a larger resistor value for RG slows down the turnon and turnoff of the MOSFET. A slower switching speed reduces EMI but also increases the switching loss. A trade-off between switching loss and EMI performance must be carefully performed.

·         LOSSES IN MOSFET :

In the ideal switching regulator shown in Figure 2, the current is zero when the switch is open and the power loss is zero, thus VIN is being chopped. When the switch is closed, the voltage across it is zero and the power loss is also zero. An ideal switch implies zero losses, thus offering 100% efficiency. An efficient switching regulator results in less heat dissipation, which reduces system cost and size for elements such as heat sinks, fans and their assembly. In batteryoperated systems, less power loss means that these devices can use the same battery for a longer run time because the device pulls less current from the battery.

MOSFETs have a finite switching time, therefore, switching losses come from the dynamic voltages and currents the MOSFETs must handle during the time it takes to turn on or of, Gate-drive losses are also switching losses because they are required to turn the FETs on and off.

Conduction loss : RDS(on) * I(sw)-(RMS)

MOSFET switching losses are a function of load current and the power supply’s switching frequency as shown by below Equation
Psw = Vin * Iout * Fsw * ((Qgs + Qgd) / Ig )
where VIN = VDS (drain-to-source voltage),
IOUT = ID (drain current),
fSW is the switching frequency,
QGS2 and QGD depend on the time the driver takes to charge the FET
 IG is the gate current.
 Switch-MOSFET gate losses can be caused by the energy required to charge the MOSFET gate. That is, the QG(TOT) at the gate voltage of the circuit. These are both turn-on and turn-off gate losses. Most of the power is in the MOSFET gate driver. Gatedrive losses are frequency dependent and are also a function of the gate capacitance of the MOSFETs. When turning the MOSFET on and off, the higher the switching frequency, the higher the gate-drive losses. This is another reason why efficiency goes down as the switching frequency goes up.Larger MOSFETs with lower RDS(on) provide lower conduction losses at the cost of higher gate capacitances, which results in higher gate-drive losses.

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Conclusion :

Power loss in a MOSFET comes from two sources. Every MOSFET has a resistive element, so it dissipates power as current is conducted through the device. The resistive parameter is described as on-resistance, or RDS(ON). These conduction losses are inversely proportional to the size of the MOSFET; the larger the switching transistor, the lower its RDS(ON) and, therefore, its conduction loss.


The other source of power loss is through switching losses. As the MOSFET switches on and off, its intrinsic parasitic capacitance stores and then dissipates energy during each switching transition. The losses are proportional to the switching frequency and the values of the parasitic capacitances. As the physical size of the MOSFET increases, its capacitance also increases; so, increasing MOSFET size also increases switching loss. 


These sources of power loss create a significant challenge for power supply designers. While a larger MOSFET will exhibit less on-resistance – and consequently lower conduction loss – its larger area drives up parasitic capacitance and switching loss. In many cases, moving to a larger MOSFET to reduce conduction loss will result in so much increased switching loss that it outweighs the conduction loss savings. Designers typically try to achieve a balance between conductive and switching losses for a particular application.







FAQ :

1) Is it possible to use the Zener diode between the gate and source for surge absorption?
The Zener diode between gate and source is intended for electrostatic breakdown protection. Please confirm whether overvoltage is applied to the gate in the actual state.


2) What does the dv/dt of the MOSFET mean?
The dv/dt of the MOSFET is the changing rate of the drain-source voltage during the switching transient.
If dv/dt is too large, ringing may occur, possibly leading to MOSFET damage.
Therefore, dv/dt ruggedness values are specified for some MOSFETs.


3) How does the series gate resistor affect the MOSFET?
When using lower gate resistance, switching time becomes shorter, and ringing (damped oscillation) may occur.
Ringing can cause oscillation and EMI noise.
When using higher gate resistance, switching time becomes longer.
As a result, switching loss increases and heat is generated.
In the bridge circuit, a short circuit may occur across the upper and lower MOSFETs by combination of the gate resistances.
Therefore, it is necessary to consider the optimum gate resistance.



4) The MOSFET does not turn off by a turn-off signal. How do I solve this problem?

Confirm whether the control signal voltage Vdrive is close to the GND or not.
When the voltage is not close to the GND, the output impedance of the gate drive circuit may be high. Consider lowering output impedance. (Select different turn off path for turning off the MOSFET quickly).
Confirm whether the gate-source voltage VGS is the same as the control signal or not. If it is not, insert a pull-down resistor Rpull between gate and source to ensure the gate-source voltage VGS to the GND level.
Please select Rpull accordinglly that does not affect the gate driving performance.




5) Is the on-state resistance of a MOSFET dependent on temperature?

The MOSFET has a positive temperature coefficient. Since values of coefficients depend on the drain-source breakdown voltages and the process, it is necessary to confirm with the data sheet etc. When performing thermal design / circuit design, please consider this temperature fluctuation.

6) Is the MOSFET drive current necessary?

For bipolar transistors, a large base current is required to maintain low on-voltage. However, since the MOSFET is a voltage control element, it can drive with small power sufficient to charge the gate. But because the input capacitance (Ciss) of the power MOSFET is rather large for high-speed switching, it is necessary to quickly charge the input capacitance with a low-impedance drive circuit.
For an indication of the gate current required for charging, it is possible to calculate the drive current simply by using the Qg characteristic prescribed on the data sheet. The required switching time is “t (desired)” (for example ton or toff), which becomes the following expression.
Ig=Qg/t(desired)



7) Are there any special considerations for using MOSFETs?

For MOSFETs, the maximum allowable current, voltage, power dissipation and other characteristics are specified as maximum ratings. Maximum ratings are the highest absolute values that must not be exceeded even instantaneously under any conditions. A device may not be able to recover from stress that exceeds a specified maximum rating. None of the absolute maximum ratings may be exceeded. Care should therefore be exercised regarding bounces in supply voltage, variations in the characteristics of electronic devices, possible exposure to stress higher than maximum ratings during circuit adjustment, changes in ambient temperature, fluctuations in the input signal, and other such factors. Please select the appropriate device according to the application.
Also, even within the absolute maximum ratings and the operating range, reliability will change significantly depending on the degree of derating



8Electrical characteristics of MOSFETs (Dynamic Characteristics tr/ton/tf/toff)

Switching characteristics
Since power MOSFETs are majority-carrier devices, they are faster and capable of switching at higher frequencies than bipolar transistors.
Switching time measurement circuit and input / output waveform are shown below.



1.      td (on): Turn-on delay time
The time from when the gate-source voltage rises above 10% of VGS until the drain-source voltage reaches 90% of VDS
2.      trRise time
The time taken for the drain-source voltage to fall from 90% to 10% of VDS
3.      tonTurn-on time
The turn-on time is equal to td (on)+ tr.
4.      td (off)Turn-off delay time
The time from when the gate-source voltage drops below 90% of VGS until the drain-source voltage reaches 10% of VDS
5.      tfFall time
The time taken for the drain-source voltage to rise from 10% to 90% of VDS
6.      toffTurn-off time
The turn-off time is equal to td(off)+ tf.

Characteristics
Symbol
Min
Typ
Max
Unit
Switching time
Rise time
tr
13
ns
Turn-on time
ton
26
Fall time
tf
14
Turn-off time
toff
63


9) Electrical characteristics of MOSFETs (Charge Characteristic Qg/Qgs1/Qgd/QSW/QOSS)

Gate charge
Because the Gate (G) input terminal of a MOSFET is insulated, the amounts of charge Q seen from the Gate are important characteristics. Figure 1.5 illustrates the definitions of gate charge characteristics.
Total gate charge Qg
The amount of charge to apply voltage (from zero to designated voltage) to gate
Gate-source charge 1 Qgs1
The amount of charge required for a MOSFET to begin to turn on (before dropping drain-source voltage)
Gate-drain charge Qgd
The amount of gate charge charged in the Miller plateau
Gate switch charge Qsw
The amount of charge stored in the gate capacitance from when the gate-source voltage has reached Vth Until the end of the Miller plateau
Output charge Qoss
Drain-source charge

The definition of the gate charge amount is shown in the figure below.


Data sheet description
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
Total gate charge
Qg
VDD ≈ 20 V, VGS = 10 V, ID = 50 A
103
nC
VDD ≈ 20 V, VGS = 4.5 V, ID = 50 A
49
Gate-source charge 1
Qgs1
VDD ≈ 20 V, VGS = 5 V, ID = 50 A
25
Gate-drain charge
Qgd
12.4
Gate switch charge
QSW
23
Output charge
QOSS
VDS = 20 V, VGS = 0 V
85.4



9) Electrical characteristics of MOSFETs (Static Characteristics RDS(ON))

Drain-source on-state resistance (RDS(ON)
The resistance across drain and source when the MOSFET is in the "on" state

VDS(ON)measurement


The specified constant drain current, ID, is applied until VGSreaches the specified voltage. At this point, drain-source voltage is measured. On-state resistance is calculated by dividing it by the value of drain current, ID.
Note: Keep the open-circuit voltage of the constant-current source below the drain-source breakdown voltage.
Measurement of forward transfer admittance

Gate-source voltage, VGS, is increased until drain current, ID, reaches the specified value. Then, VGSis changed only slightly, and the resulting change in drain current, ID, is measured.


Data sheet description
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
Drain-source on-state resistance
RDS(ON)
VGS = 4.5 V, ID = 50 A
0.95
1.35
VGS = 10 V, ID = 50 A
0.65
0.80



10) Electrical characteristics of MOSFETs (Static Characteristics Vth)

Gate threshold voltage (Vth)
Vth stands for "threshold voltage." Vth is the gate voltage that appears when the specified current flows between source and drain.
Vth measurement :


Gate-source voltage, VGS, is increased until drain current, ID, reaches the specified value, at which point VGSis measured.

Data sheet description
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
Gate threshold voltage
Vth
VDS = 10 V, ID = 1.0 mA
1.4
2.4
V



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Author:
 JAYDEEP SHAH (E.C )
AHMEDABADN – INDIA